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1st Semester
Digital Logics
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1st Semester
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Lab 1
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Table of Index
S.N.
Lab Objective
Date
Signature
1
2
3
4
5
6
To verify truth table of Basic Gates
To verify truth table of NAND and NOR Gates
To verify truth table of HALF ADDER and HALF SUBTRACTOR
To verify truth table of FULL ADDER and FULL SUBTRACTOR
To verify truth table of Encoder and Decoder via simulator
To verify truth table of Multiplexer (1:8 MUX) and Demultiplexer (8:1 DEMUX) via Simulator